The present invention relates to a semiconductor memory device, and in particular, to a technology effectively applicable to, for example, a static random access memory (RAM) and the like.
A memory cell of a static RAM using a metal oxide semiconductor field effect transistor (MOSFET) includes, as a basic configuration, a static flip-flop circuit comprising, for example, a pair of driving MOSFETs in which the gates and drains thereof are crosswisely connected with each other and load means disposed on each drain. The drain region of each driving MOSFET is further connected via a transmission gate MOSFET to a data line in a respective pair of complementary data lines, thereby establishing input/output nodes of the memory cell.
A read signal fed from a selected memory cell is transmitted via the pair of complementary data lines and is amplified by means of a sense amplifier circuit using, for example, a differential MOSFET.
On the other hand, there has been a digital processor of the 1-chip type having a built-in static RAM the. In such a digital processor, the static RAM is used, for example, as an arithmetic register and a stack memory. In this case, the processing throughout the digital processor varies depending on the access time of the static RAM integrated therein. To overcome this difficulty, as a method to increase the processing throughout the digital processor by improving the access speed of the static RAM, the half precharge method has already been proposed by Hitachi, Ltd. (the assignee of the present invention; Ser. No. 943,063, now abandoned (M. Uchida)) in which the complementary data lines are charged to a level which is 1/2 of the power source voltage Vcc.
FIGS. 9-10 which relate to copending and commonly assigned U.S. patent application Ser. No. 943,063, filed Dec. 18, 1986, now abandoned, and Ser. No. 212,575, filed June 28, 1988, which is a continuation of Ser. No. 860,411, filed May 7, 1986, now U.S. Pat. No. 4,758,990, are an example of a circuit diagram and a timing chart of the read operation, respectively of a precharge circuit for the static RAM utilizing the precharge method described in the application. In FIG. 9, the input/output nodes of each memory cell MC are respectively connected with a pair of complementary data lines D0 and D0 (D1 and D1). The noninverting signal line D0 (D1) of the pair of complementary data lines D0 and D0 (D1 and D1) is connected via the MOSFET Q19 (Q21) to the power source volatage Vcc, whereas the inverting signal line D0 (D1) thereof is connected via the MOSFET Q20 (Q22) to a grounding potential. Between the noninverting signal line D0 (D1) and the inverting signal line D0 (D1) of the pair of complementary data lines, there is disposed the MOSFET Q27 (Q28) for providing a short circuit (equalization). The gates of the MOSFETs Q19-Q22 are provided with a precharge signal .phi.pc, which is set to the high level when the static RAM is in other than the selected state and which is set to the low level when the static RAM is in the selected state. The gates of the MOSFET Q27-Q28 are supplied with a timing signal .phi.eq, which is temporarily set to the high level at the activation of the static RAM. When the static RAM is set to other than the selected state, the noninverting signal line D0 (D1) and the inverting signal line D0 (D1) of the respective pair of complementary data lines are charged to the power source voltage Vcc and the grounding potential of the circuit, respectively. Moreover, since the noninverting signal line D0 (D1) and the inverting signal line D0 (D1) of the respective pair of complementary data lines are short circuited at the initiation of the static RAM, the charge levels thereof are set to the half precharge level, i.e. Vcc/2. This enables increasing the read signal margin and the read speed of the static RAM.